1. Field of the Invention
This invention relates to a liquid crystal display, and more particularly to a liquid crystal display and a driving method thereof wherein a frame can be driven by multiplying a frame frequency while keeping the brightness identical to brightness for the non-multiplied frame driving.
2. Description of the Related Art
Generally, a liquid crystal display (LCD) controls light transmittance of liquid crystal cells in accordance with video signals to thereby display a picture. An active matrix type of liquid crystal display device having a switching device provided for each liquid crystal cell is advantageous for displaying a moving picture because it permits an active control of the switching device. The switching device used for the active matrix liquid crystal display device is generally a thin film transistor (TFT) as illustrated in FIG. 1.
Referring to FIG. 1, the active matrix LCD converts a digital input data into an analog data voltage on the basis of a gamma reference voltage to supply it to a data line DL and, at the same time, supplies a scanning pulse to a gate line GL to thereby charge a liquid crystal cell Clc.
A gate electrode of the TFT is connected to the gate line GL while a source electrode of the TFT thereof is connected to the data line DL. Further, a drain electrode of the TFT is connected to a pixel electrode of the liquid crystal cell Clc and to one electrode of a storage capacitor Cst.
A common electrode of the liquid crystal cell Clc is supplied with a common voltage Vcom.
The storage capacitor Cst functions to charge a data voltage fed from the data line DL when the TFT is turned on, thereby constantly maintaining a voltage at the liquid crystal cell Clc.
If the scanning pulse is applied to the gate line GL, then the TFT is turned on to provide a channel between the source electrode and the drain electrode, thereby supplying a voltage on the data line DL to the pixel electrode of the liquid crystal cell Clc. At this time, liquid crystal molecules of the liquid crystal cell has an alignment changed by an electric field between the pixel electrode and the common electrode to thereby modulate an incident light.
A configuration of the related art LCD including pixels having the above-mentioned structure will be described with reference to FIG. 2.
FIG. 2 is a block diagram illustrating a configuration of a general liquid crystal display device.
Referring to FIG. 2, a general liquid crystal display device 100 includes a liquid crystal display panel 110 provided with a plurality of thin film transistors (TFT) at crossing points of data lines DL1 to DLm and gate lines GL1 to GLn for driving the liquid crystal cells Clc, a data driver 120 for supplying a data to the data lines DL1 to DLm of the liquid crystal display panel 110, a gate driver 130 for supplying a scanning pulse to the gate lines GL1 to GLn of the liquid crystal display panel 110, a gamma reference voltage generator 140 for generating a gamma reference voltage to supply it to the data driver 120, a backlight assembly 150 for irradiating a light onto the liquid crystal display panel 110, an inverter 160 for applying an alternating current voltage and a current to the backlight assembly 160, a common voltage generator 170 for generating a common voltage Vcom to supply to the common electrode of the liquid crystal cell Clc of the liquid crystal display panel 110, a gate driving voltage generator 180 for generating a gate high voltage VGH and a gate low voltage VGL to supply them to the gate driver 130, and a timing controller 190 for controlling the data driver 120 and the gate driver 130.
The liquid crystal display panel 110 has a liquid crystal between two glass substrates. On the lower glass substrate of the liquid crystal display panel 110, the data lines DL1 to DLm and the gate lines GL1 to GLn perpendicularly cross each other. Each crossing of the data lines DL1 to DLm and the gate lines GL1 to GLn is provided with the TFT. The TFT supplies a data on the data lines DL1 to DLm to the liquid crystal cell Clc in response to the scanning pulse. The gate electrode of the TFT is connected to the gate lines GL1 to GLn, while the source electrode thereof is connected to the data line DL1 to DLm. Further, the drain electrode of the TFT is connected to the pixel electrode of the liquid crystal cell Clc and to the storage capacitor Cst.
The TFT is turned on in response to the scanning pulse applied, via the gate lines GL1 to GLn, to the gate terminal thereof. Upon turning-on of the TFT, video data on the data lines DL1 to DLm is supplied to the pixel electrode of the liquid crystal cell Clc.
The data driver 120 supplies data to the data lines DL1 to DLm in response to a data driving control signal DDC from the timing controller 190. Further, the data driver 120 samples and latches a digital video data RGB fed from the timing controller 190, and then converts it into an analog data voltage capable of expressing a gray scale level at the liquid crystal cell Clc of the liquid crystal display panel 110 on a basis of a gamma reference voltage from the gamma reference voltage generator 140, thereby supplying it the data lines DL1 to DLm.
The gate driver 130 sequentially generates a scanning pulse, that is, a gate pulse, in response to a gate driving control signal GDC and a gate shift clock GSC from the timing controller 190 to supply them to the gate lines GL1 to GLn. At this time, the gate driver 130 determines a high level voltage and a low level voltage of the scanning pulse in accordance with the gate high voltage VGH and the gate low voltage VGL from the gate driving voltage generator 180.
The gamma reference voltage generator 140 receives a high-level supply voltage VDD to generate a positive gamma reference voltage and a negative gamma reference voltage and output them to the data driver 120.
The backlight assembly 150 is provided at the rear side of the liquid crystal display panel 110, and is energized by an alternating current voltage and a current supplied to the inverter 160 to irradiate light onto each pixel of the liquid crystal display panel 110.
The inverter 160 converts a rectangular wave into a triangular wave signal and then compares the triangular wave signal with a direct current power voltage Vcc supplied from said system, thereby generating a burst dimming signal proportional to a result of the comparison. If the burst dimming signal determines in accordance with the rectangular wave signal at the interior of the inverter 160, then a driving integrated circuit (IC), as not illustrated, for controlling a generation of the AC voltage and current within the inverter 160 controls a generation of AC voltage and current supplied to the backlight assembly 150 in response to the burst dimming signal.
The common voltage generator 170 receives a high-level power voltage VDD to generate a common voltage Vcom and supplies it to the common electrode of the liquid crystal cell Clc provided at each pixel of the liquid crystal display panel 110.
The gate driving voltage generator 180 is supplied with a high-level power voltage VDD to generate the gate high voltage VGH and the gate low voltage VGL, and supplies them to the data driver 130. Herein, the gate driving voltage generator 180 generates a gate high voltage VGH more than a threshold voltage of the TFT provided at each pixel of the liquid crystal display panel 110 and a gate low voltage VGL less then the threshold voltage of the TFT. The gate high voltage VGH and the gate low voltage VGL generated in this manner are used for determining a high level voltage and a low level voltage of the scanning pulse generated by the gate driver 130, respectively.
The timing controller 190 supplies a digital video data RGB from a digital video card (not shown) to the data driver 120 and, at the same time, generates a data driving control signal DCC and a gate driving control signal GDC using horizontal/vertical synchronizing signals H and V in response to a clock signal CLK to supply them to the data driver 120 and the gate driver 130, respectively. The data driving control signal DDC includes a source shift clock SSC, a source start pulse SSP, a polarity control signal POL and a source output enable signal SOE, etc. The gate driving control signal GDC includes a gate start pulse GSP and a gate output enable signal GOE, etc.
The liquid crystal display device 100 having the above-mentioned configuration and function is typically driven with a frequency of 60 Hz. However, there have been recently developed a technique of driving the liquid crystal display device 100 with a frequency of 120 Hz in order to eliminate a stain at the moving picture.
When the liquid crystal display device 100 is driven with 120 Hz, a gray data conversion is carried out, while allowing an average brightness of two frames to equally keep a brightness of one frame when the liquid crystal display device 100 is driven with 60 Hz. In this case, there is raised a disadvantage in that, because a high gray and a low gray is alternately displayed on the screen, a flicker can be viewed by human eyes.